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| ispPAC-POWR1208 Evaluation Board PAC-POWR1208-EV April 2004 Application Note AN6040 Introduction The Lattice Semiconductor ispPAC(R)-POWR1208 In-System-Programmable Analog Circuit allows designers to implement both the analog and digital functions of a power supply monitoring and sequencing subsystem within a single integrated circuit. By integrating analog functions such as comparators and programmable slew rate FET drivers with the digital functionality of a Programmable Logic Device (PLD), the ispPAC-POWR1208 provides the power-supply designer with a rich set of features in a single device. ISPTM (In-System-Programmability) provides the designer with an unprecedented level of flexibility, allowing him to configure analog parameters such as threshold voltages as well as defining state machines and combinatorial logic functions. All configuration data is stored internally in E2CMOS(R) nonvolatile memory. Programming a configuration is accomplished through an industry-standard JTAG IEEE 1149.1 interface. PAC-POWR1208-EV Evaluation Board The PAC-POWR1208-EV evaluation board (Figure 1) allows the designer to quickly configure and evaluate the ispPAC-POWR1208 on a fully assembled printed-circuit board. The double-sided board supports a 44-pin TQFP package, a header for user I/O, a JTAG programming cable connector, and an uncommitted pad array for user prototyping. JTAG programming signals can be generated by using an ispDOWNLOAD(R) programming cable connected between the evaluation board and a PC's parallel (printer) port. Both analog and digital features of the ispPAC-POWR1208 can be easily configured using PAC-Designer(R) software. Figure 1. PAC-POWR1208-EV Evaluation Board www.latticesemi.com 1 an6040_01 Lattice Semiconductor ispPAC-POWR1208 Evaluation Board PAC-POWR1208-EV A complete schematic for the evaluation board is shown in Figure 2. Figure 2. Schematic VDD VDDINP VDD R1B 470 C5 4.7U C1 0.1U J7.5 C3 0.1U R1D 470 5 VDD CLK VDDINP 26 CLK 12 OUT5 OUT6 VDDINP VDD VDD R2 10K RESET SW1 Reset C4 0.1U 10 RESET J7.1 J7.2 J7.3 J7.4 VDD VDDINP OUT7 OUT8 13 14 15 OUT5 OUT6 OUT7 OUT8 11 VDDINP LED OUT5 LED OUT6 R1E 470 R1F 470 LED OUT7 LED OUT8 R1G 470 R10 2k R9 2k R8 2k R7 2k J9 VDDINP LED POWER ispPAC-POWR1208 POR 25 32 33 34 35 36 37 38 POR HVOUT1 4 3 2 1 R3 2k R4 2k R5 2k R6 2k J8 HVOUT1 HVOUT2 HVOUT3 HVOUT4 P5 VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 VMON7 VMON8 VMON9 VMON10 VMON11 VMON12 IN1 IN2 IN3 IN4 VDD VDD TDI VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 HVOUT2 HVOUT3 HVOUT4 VMON7 40 VMON8 41 VMON9 42 VMON10 43 VMON11 44 VMON12 6 7 8 9 IN1 IN2 IN3 IN4 TDI 30 TCK 24 TMS 31 TDO 28 COMP1 COMP2 COMP3 COMP4 COMP5 COMP6 COMP7 COMP8 CREF GND 27 23 22 21 20 19 18 17 16 39 C2 1U VDD TDO LED R1C 470 COMP1 COMP2 COMP3 COMP4 COMP5 COMP6 COMP7 COMP8 S CH VDD TDI TDO TMS TCK GND P1 TDO TMS TCK GND Programming Interface Lattice Semiconductor's ispDOWNLOAD(R) cable can be used to program the ispPAC-POWR1208 on the evaluation board. This cable plugs into a PC-compatible's parallel port connector, and includes active buffer circuitry inside its DB-25 connector housing. The other end of the ispDOWNLOAD cable terminates in an 8-pin 0.100" pitch header connector which plugs directly into a mating connector provided on the PAC-POWR1208-EV evaluation board. Prototype Area A 19x18 grid (0.100" pitch) of uncommitted, plated through holes with annular-ring pads is provided as a user prototyping area. Adjacent to this uncommitted array are two 19-hole rows providing easy connections to both power and ground. This prototyping area allows the user to build small circuits directly on the evaluation board. In the case of larger circuits, the evaluation board can be readily connected into off-board circuitry through P5, into which can be mounted a 20 x 2 header. Power Supply Considerations The ispPAC-POWR1208 operates with power supplies ranging from 2.25V to 5.5V, and allows for separate core (VDD) and I/O (VDDINP) voltages. Voltages ranging from 0 to 5.75V may be monitored at any of the 12 VMONx pins independent of the values of VDD and VDDINP. For device programming, however, VDD MUST be set to 3.3V. 2 P2 P5 Lattice Semiconductor ispPAC-POWR1208 Evaluation Board PAC-POWR1208-EV On the evaluation board, VDD and VDDINP are normally connected together with a user-removable jumper (J7.5). This jumper can be removed to allow for independent VDD and VDDINP supplies. Input/Output Connections Connectors are provided for key functions and test points on this evaluation board, as shown In Figure 3. Power is supplied through two color coded (RED = +, BLACK = -) banana jacks in the upper right corner of the board. The JTAG programming cable is connected to a keyed header (P1) in the lower right corner of the board. A PCB land pattern is provided for the addition of an additional JTAG interface header (P2) to allow for connecting multiple PAC-POWR1208-EV evaluation boards into a multi-device programming chain. Access to the ispPAC-POWR1208's I/O pins is available at P5, which is a 2x20 row of pads to which one may attach test probes or a ribbon-cable connector. At this point all of the device's I/O pins (except those required for the JTAG programming interface) are accessible. Figure 3. I/O and Jumpers J9 VDD OUT[5-8] VDDINP J8 VDD HVOUT[1-4] VDDINP J7 HVOUT PULL-UP 1234 VDD VDDINP VDD GND P5 VMON1 VMON3 VMON5 VMON7 VMON9 VMON11 HVOUT4 HVOUT2 VDD IN2 IN4 VDDINP GND OUT5 OUT7 COMP8 COMP6 COMP4 COMP2 POR VMON2 VMON4 VMON6 VMON8 VMON10 VMON12 HVOUT3 HVOUT1 IN1 IN3 RESET GND GND OUT6 OUT8 COMP7 COMP5 COMP3 COMP1 CLK ispPACPOWR1208 OUT8 OUT7 OUT6 OUT5 RESET Power TDO P1 JTAG Interface 1 Jumper Options Several jumpers are provided on the evaluation board to make it simple to implement common circuit configurations. These jumpers are: * J7 - positions 1-4 connect pull-up resistors to the high voltage outputs HVOUT1-4, and allow the user to enable the pull-ups on an output-by-output basis. The pull-up voltage is selected by J8. Position 5 (the rightmost position) is used to connect VDDINP to VDD, and should normally be left in place. This jumpers needs to be removed when using separate VDD and VDDINP supplies. * J8 - Selects a pull-up voltage to which the High-Voltage outputs (HVOUT1-4) may be pulled up to, either VDD or VDDINP. * J9 - Selects whether open-drain digital outputs OUT5-OUT8 are pulled up to VDD (upper position), VDDINP (lower position), or not pulled up at all. These outputs are pulled up through 2K resistors. 3 Lattice Semiconductor ispPAC-POWR1208 Evaluation Board PAC-POWR1208-EV Controls and Indicators A reset switch is provided on the evaluation board which pulls the RESET input pin low when it is depressed, re-initializing the ispPAC-POWR1208. LEDs are also provided as an aid to debugging. One LED shows whether the board has power applied, while another is connected to the JTAG TDO line, and will flash when a download is being performed. Additionally, four LEDs are attached to the ispPAC-POWR1208's OUT5-OUT8 lines. By adding appropriate code to the sequencer program, these LEDs can be made to indicate the internal status of the ispPAC-POWR1208, and can be a useful debug aid. PCB Artwork Figure 4. Silk Screen 4 Lattice Semiconductor Figure 5. Top-side Foil ispPAC-POWR1208 Evaluation Board PAC-POWR1208-EV Figure 6. Bottom-side Foil 5 Lattice Semiconductor ispPAC-POWR1208 Evaluation Board PAC-POWR1208-EV Component List Quantity 2 1 1 1 1 2 5 1 1 1 1 1 8 1 1 1 C1, C3 C2 C4 C5 J7 J8,J9 LED_A, LED_B, LED_C, LED_D, POWER_LED P1 P3 P4 R1 R2 R3, R4, R5, R6, R7, R8, R9, R10 SW3 TDO_LED U1 Ref. Designators 0.1F capacitor 1F capacitor 0.1F capacitor 4.7F capacitor 2 x 5 header strip, dual row, 0.1" spacing 1 x 3 header strip, single row, 0.1" spacing T-1-3/4 red LED 1x8 header strip, single row, 0.1" spacing Red banana jack Black banana jack 470 ohm SIP-8 resnet, 7-resistor SIP, bussed type 10K resistor 2K 5% resistor Pushbutton switch T1-3/4 green LED ispPAC-POWR1208 Description Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-408-826-6002 (Outside North America) e-mail: isppacs@latticesemi.com Internet: www.latticesemi.com 6 |
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